1. Field of the Invention
The present invention relates to a non-volatile memory and the manufacturing method thereof. More particularly, the present invention relates to a one time programmable memory and the manufacturing method thereof.
2. Description of Related Art
Non-volatile memories can be classified into mask ROM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (E2PROM), one time programmable ROM (OTPROM) etc. based on the data writing manners thereof.
The U.S. Pat. No. 6,678,190 discloses a one time programmable read-only memory, wherein two P-type transistors disposed on N-well and connected in series are respectively used as the select gate and the floating gate. This invention can be integrated with CMOS fabricating process since no control gate is required.
However, faster and smaller products have been developed along with the development of the IC industry; thus, the integration of semiconductor devices has to be increased continuously. The decrease in line width will result in too small channel current in the memory, accordingly, data misjudgment is easily induced and the reliability of the memory is reduced.
In addition, misalignment can be easily induced in etching process of contact window opening due to the increase in the integration of the devices, so that the contact window opening may be etched to the isolation structure besides the doped region, which may result in PN junction between the P-type doped region and the N-well and further the problem of current leakage.
To avoid the aforementioned PN junction problem, a silicon nitride layer is usually formed on the isolation structures for preventing over-etching. However, a part of the charges stored in the floating gate may diffuse into the silicon nitride layer due to the charge trapping characteristic of silicon nitride, which may result in too small channel current and may reduce the operation efficiency of the memory.